FIG. 1 shows a standard prior art implementation of a summing comparator. The device of FIG. 1 includes integrators 20 and 22; summing amplifier 24; comparator 26; resistors RI, RF, RZ; capacitors CI and CZ; DC reference voltage 28; common mode voltages VCM1 and VCM2; integrator 20 output Vp; integrator 22 output Vm; and source voltage nodes VDDA and GND. The outputs of integrators 20 and 22 are summed using a buffer or some kind of an instrumentation amplifier (summing amplifier 24) and then the sum is compared to a DC reference voltage 28 or ground GND by comparator 26. As long as this output is greater than the DC reference voltage, the comparator 26 switches. The disadvantage with this method is that it needs summing amplifier 24. Such an implementation is area expensive and consumes more power. In the implementation shown in FIG. 8, the comparator switches when
            V      p        >          V      m        ⇒            (                                    -            K                    s                -                              K            2                                s            2                              )        >    0    ⇒                    -        K            s        >                  K        2                    s        2            Where
      -    K    srepresents the output of integrator 20 at node Vp,
      K    2        s    2  represents the output of integrator 22 at node Vm,
            -      K        s    -            K      2              s      2      represents the output of summing amplifier 24, and the DC reference voltage is ground.